Low-Power Electronics Redraw Satellite Design
Radiation-tolerant chips that run on a half volt could extend space vehicles’ operational lives.
Microprocessors capable of operating at extremely low power levels will soon fly in a variety of spacecraft. Radiation hardened in a novel process that allows them to be produced in existing facilities, the chips will play a role in future near-earth and deep-space missions. Moreover, the technology presents potential applications beyond aerospace circles, especially in battery-powered communications devices, sensors and portable electronics.
Managing limited power supplies has always been a critical issue in space vehicle design. Because most systems employ a combination of solar cells and battery power, the amount of energy consumed by electronics in areas such as avionics, science experiments or communications can lead to operational limitations. Drastic reductions in power demand alter this formula, freeing engineers to create craft with dramatically different configurations because increased battery life results in smaller solar panels and smaller satellites. The same principles used in space flight can be applied to terrestrial technologies such as cellular telephones or the host of wireless data devices soon to enter commercial and government markets.
Scientists at the University of New Mexico’s Microelectronics Research Center in Albuquerque developed the microchips as part of a program funded by the National Aeronautics and Space Administration (NASA) and the National Reconnaissance Office (NRO). The program’s purpose is to find new ways to design low-power technologies for spacecraft electronics.
According to Capt. William Cashman, USAF, project manager of the NRO’s ultralow power chip program, the agency was drawn to the technology because of the promise to dramatically reduce satellite power demands. “If you can reduce the power that’s required on a spacecraft, you can either put more capability up there for the same kind of budget or you can reduce spacecraft size and save money that way,” he says.
The ultralow power (ULP) complementary metal oxide semiconductor (CMOS) chips differ from standard electronics because they operate at a considerably lower level than current microprocessors—0.5 volts compared to 5 volts. According to Gary Maki, director of the University of New Mexico’s Microelectronics Research Center, this savings is achieved through a lower supply voltage. Lower power can also be achieved in normal CMOS chips by lowering the voltage, but this will affect performance. The ability to operate at reduced-threshold voltages—the minimum amount of power required to turn a transistor on—is what sets these chips apart, he says.
The transistors are modified to operate within lower energy thresholds, allowing for faster operation. The result is lower power due to lower voltage, but performance is maintained because of the transistors’ new characteristics. The processors do not operate as fast as cutting-edge chips; however, this is not a disadvantage in spacecraft design where radiation tolerance is an issue, Maki explains.
One problem spacecraft face is latchup, an event caused when a charged particle lodges in a chip’s gate array and effectively keeps a set of junctions in a device turned on. This can seriously damage electronics through overheating unless the system is shut down and restarted—something that can be fatal to a deep-space probe because it can take half an hour or more for news of a malfunction to reach ground control. One way to avoid the problem is to use older chips with larger gate sizes because performance can be enhanced by rewriting operating software.
A key feature of the CMOS ultralow power radiation tolerant (CULPRiT) technology is a special gate structure designed to prevent latchup. It consists of two transistors working together. If there is no failure, one transistor produces a one and the other a zero, creating a feedback loop between the two networks. A particle hitting either structure will create an opposite, or false, reading that is detected and corrected by a buffer that only recognizes a correct signal from each transistor. The techniques used to create the gates are circuit, not process methods, Maki notes. Because of this, the chips can be manufactured in existing facilities without modifying the production process.
The procedure involves changing four steps in the chip-making process, primarily in areas where implants are done with the threshold voltages. These are changed from standard to ULP technology. This can be done on a bulk CMOS process on a commercial line.
Low power consumption also protects against latchup. Current chips operate at 5 volts, with next-generation models that are now becoming available running on 3.3 volts. Beyond these, microprocessors from some advanced foundries use only 1.8 volts. However, they still require more energy than CULPRiT devices. When these power levels are combined into the multiple processors and systems commonly found on a spacecraft, they add up to considerable power savings. By its own estimates, the semiconductor industry does not plan to approach the half-volt threshold until some time after 2010, Maki says.
The chips currently are being tested for radiation resistance. According to Maki, NASA guidelines call for a device to withstand a total dose of 200 kilorads. It must also possess a single-event-upset immunity and a linear-energy-transfer tolerance greater than 40. Maki notes that most satellites experience 200 kilorads from particles moving through the Earth’s magnetic field and the Van Allen radiation belts formed around the Earth by high-energy charged particles that are trapped by the geomagnetic field. This radiation buildup accumulates over time.
Radiation testing is being conducted at Lawrence Livermore Laboratories in Livermore, California, and at Brookhaven National Laboratories in Upton, New York. According to Geoff Summers, a research physicist with the Naval Research Laboratory (NRL) in Washington, D.C., trials will be conducted with a laser and a particle accelerator. The Brookhaven accelerator has a single-event-effect attachment that is widely used by NASA and other agencies. The NRL will conduct tests using a laser, which is less expensive to operate than a particle accelerator and can simulate the deposition of energy made by a charged particle as it passes through the chip. The laser can also be pulsed to coincide with certain cycles in the chip and target specific areas in the device.
Because the chips operate at low power, they already have a built-in immunity to total dose radiation, Summers says. The technique used to control the threshold voltage, which he describes as a back bias, makes them resistant or tolerant to more than 200 kilorads. This is not a specific process but rather a side effect of the power-saving effort. The gate mechanisms, which are a single-event-upset mitigation scheme, have already been used successfully on standard chips in the Hubble space telescope and in the space shuttle fleet, Summers explains. It is this same method that has been put into the ULP chips.
“Ultralow voltage transistors should be immune because CMOS latchup is caused by parasitic transistors that develop in the circuit, and when you get below the turn-on voltage of a silicon diode—which is about 0.7 or 0.8 volts—the transistors cannot turn on. So if you are at 0.5 volts, for example, you are intrinsically latchup immune, which is another reason you would want to go this way,” Summers says. However, he adds that while tests have not yet been conducted on the latest batch of chips, in principle the technology should be latchup immune.
Important aspects of the technology are its applicability to existing chips and the ability to manufacture the chips in foundries without modifying production procedures. Maki notes that the first batch of chips was produced in March 1999. A second batch of chips, being used in the radiation particle tests, was produced in February.
The technology has potential uses across a variety of sectors, Capt. Cashman says. “This is something that in its full form—ultralow power and radiation tolerant—could apply to commercial space as well. Even if you were to take the radiation tolerance away and look at the ULP, that should have a number of applications across the U.S. Defense Department and commercial industry. This is something we would absolutely like to push to the broader industrial base, if we can then take advantage of it when we need it,” he says.
Because ULP devices can be made in existing facilities, production costs are reduced due to the economies of scale involved, Maki says. The number of chips needed by NASA and the NRO is relatively small—several wafers from a run of hundreds. The company manufacturing the wafers simply can add the ULP chips onto the end of a production run. Costs also are kept down because the government does not have to go to a specialty shop when it needs small numbers of chips. Maki notes that in the arrangement between the foundry and the government, 99 percent of the expense is being absorbed by the commercial side, with the government being responsible for less than 1 percent. Because the commercial foundry is responsible for the infrastructure costs, taxpayer money is saved, he says.
The chips are not completely ready for flight testing, however. Certain infrastructure issues and processes have not been fully fleshed out with the foundry, Maki allows. He believes the devices are still in the research and development phase that exists before full production runs can be ordered or the process can be handed off to other researchers.
Three fabrication runs of the chips have taken place to date, Summers states. A standard version flew on the space shuttle. He notes that the latest run contains an improved or optimized Reed Solomon encoder in both radiation tolerant and unhardened versions.
Other developments include a C50 digital signal processor for Texas Instruments as part of a joint Office of Naval Research/NRO project. It will be produced in the next run. In that batch, an 8051 microprocessor being developed for NASA Langley will be made, Summers says.
The foundry, which is owned by AMI Incorporated, Pocatello, Idaho, usually produces between 10 and 20 of the 8-inch wafers for the government. These wafers result in many chips because the dies used to make them are 13 to 14 millimeters on a side, which allows more than enough microprocessors to meet NASA’s and the NRO’s needs. However, Summers notes, “Often, you don’t want to have 10 million of these things. You may only want 100. On a typical 8-inch wafer, you get thousands. So most foundries don’t want to run when there is only one wafer involved.”
The solution is that AMI may use the production process, but the government retains guaranteed access to the production line. “So, if we want to make 10 devices, we make them,” Summers says. Because the government owns the process and developed it under federal funding, it also can move to another foundry, he observes.
Manufacturing ULP chips in commercial foundries also saves money because it would be expensive to have limited runs on government-owned production lines, Summers explains. This method allows production to be moved wherever the government wishes.
Summers adds that the program has the computer-aided design tools and software in place to take an existing circuit and rewrite it into a ULP circuit. This allows the government to have standard cell libraries that can be drawn on to produce the devices as needed. However, he cautions that this system is still under development and is not yet fully in place.
The technology provides designers with new ways to configure spacecraft, Summers says. He cites a study conducted under funding from the Johns Hopkins Applied Physics Laboratory that examined the savings that ULP electronics would realize in an actual system. The results range from 25 to 40 percent. The real issue is what this does to a complete vehicle.
“You have to start thinking differently because if you do not have to use as much power in the processing, then you do not require large solar panels, or you could either use more processing or have a smaller satellite. If you have a smaller satellite, you can have smaller solar panels. If you have smaller panels, you can have smaller gimbals because you do not have to move as much around in space. So you need less fuel to keep [it] oriented. It adds up,” Summers concludes.