Low-Power Electronics Advance to Prime Time

October 1999
By Henry S. Kenyon

Once a specialized niche technology, silicon-on-insulator chips will soon appear in a wide variety of applications.

New production methods allow constructing semiconductors capable of operating at a fraction of the power of existing devices while delivering comparable or superior performance. These new technologies could lead to extremely efficient electronic devices, from handheld computers to tactical radios and missile warheads. The potential also exists for increased processor speeds in both military and civilian communications and computing applications.

The new processes originated from a recent Defense Advanced Research Projects Agency (DARPA) program aimed at developing low-power electronics for defense and civilian uses. The two primary contractors on the project, IBM Microelectronics, East Fishkill, New York, and the Massachusetts Institute of Technology (MIT) Lincoln Laboratory, Lexington, have developed two complementary technologies and are now preparing to take their work to the production lines.

IBM has developed a partially depleted silicon-on-insulator (SOI) process that it is now deploying to manufacture chips, according to Daniel J. Radack, program manager at DARPA’s microsystems technology office, which helped fund some of the research.

The MIT Lincoln Laboratory is pursuing a fully depleted SOI technology, which, he believes, is still primarily research oriented.

Both procedures are complementary, though debate is ongoing in the research community as to which is more easily manufactured, Radack says. SOI technology puts layers of silicon on an insulating oxide. When circuits and gates are etched into the wafer, they are cut down to the insulator, which greatly reduces parasitic power loss associated with semiconductors. The terms partially and fully depleted refer to the channel region of a transistor. In both methods, the source and drain regions are depleted down to the oxide. Channel depth is where the two approaches differ. Partially depleted SOI channels are not depleted down to the oxide, while those in fully depleted chips are.

The variance in channel depth provides a big difference when it comes to performance, Dr. Craig L. Keast, leader of the advanced silicon technology group at MIT’s Lincoln Laboratory, says. The buried oxide in the depleted regions reduces power drain in both types of SOI chips. According to Keast, this allows for a steeper subthreshold slope, which determines how quickly a transistor can be turned on and off. But fully depleted semiconductors have an edge in performance. He explains that, for a bulk or partially depleted device, 85 to 95 millivolts are needed to go through a gate to initiate a charge in the device. A fully depleted device, however, can become charged with only 65 to 70 millivolts. Fully depleted devices also have a lower threshold voltage and thus a decreased power supply, Keast relates. For example, a fully depleted 400-millivolt device operates at 2 volts, while a partially depleted one needs a 600-millivolt threshold to operate at 3 volts.

One of the reasons MIT followed fully depleted SOI was that the technology is close to a device’s full theoretical performance threshold, Keast continues. But partially depleted SOI has its advantages as well. Because the silicon film is thicker—1,500 angstroms compared to 500 angstroms for fully depleted wafers—the chips are easier to manufacture. He notes that IBM has been developing partially depleted wafer technology since 1995.

SOI is about 20 years old, Keast observes. He notes that Honeywell has worked with the technology for years, producing a number of applications such as hardened chips for use in satellites and spacecraft. SOI-based devices are valued in specialized niches such as the space industry because they can operate in extremes of temperature and radiation. The new production developments by IBM, MIT and the other contractors involved in the DARPA project allow SOI’s use throughout the civilian and military markets. Keast believes that most companies with commercial or military space applications will eventually use the technology.

Material quality was one of the biggest hurdles in producing SOI chips, Keast says. Part of the DARPA program examined the process and developed technologies to improve wafer quality and reduce costs. Project staff approached this issue through a process called separation by ion implanted oxygen.

In manufacturing silicon wafers, cost is directly related to the amount of time it takes to implant wafers and anneal them to form oxide. Radack notes that the standard process uses three separate oxidations and annealings. One of the project’s goals was to invent new ways to create the same structures at lower costs. Scientists then made a major effort to reduce the process to one oxygen implantation and one annealing. Ibis Technology Corporation performed this work for IBM, he adds.

On a parallel track, researchers used a large matrix of implantation and oxidation conditions to determine the ideal conditions to construct large circuits, which was another primary project goal. Experimental wafers were produced and tested for imperfections at IBM’s production facilities. Constructing large circuits with SOI technology had never been done prior to this program, Radack says. He adds that the ability to manufacture complex devices was one of the major developments based on the research. To demonstrate this capability, IBM then produced a prototype 4-megabit static random access memory chip using SOI technology.

But finding the right dose of gases for an SOI chip proved elusive. Researchers discovered that the process window for a single implanting and annealing was much smaller than anticipated, Radack explains. Experiments with a variety of temperatures, ramp times, ambience and gases determined that the wafers required precise specifications in order to form properly. The vapors would not yield without proper implantation temperature, precise dosage and exact annealing conditions, he allows.

Radack is cautious about discussing any potential drawbacks to chips produced through depleted or semidepleted SOI processes because there is still little performance history available. The technology has passed most of its qualification hurdles, but not much reliable information exists, he says.

One concern about SOI is that the threshold voltage becomes sensitive to silicon thickness, which may cause problems such as irregularities in voltage distribution throughout a chip, Keast says. However, he adds that silicon film uniformity technology is much better now, and because of these new developments, many of the old cost- and quality-related arguments against SOI are disappearing.

The kink effect is another complication affecting SOI chips around which designers had to work. Kinking is a parasitic feedback effect that causes a spike, or kink, in voltage. Traditionally, this phenomenon was suppressed by adding a body contact to the semiconductor. According to Keast, IBM spent a great deal of design time to avoid kinking its new partially depleted chips. But the company also exploited the effect to improve overall chip performance, he explains.

Beyond power savings, another aspect of SOI technology is that each device on the chip is naturally separated, with each device sitting in its own little island, which can simplify some isolation technologies. This characteristic offers the potential for use in mixed applications such as placing separate analog and digital sections on a single chip, Radack says. Some questions do exist about the feasibility of building high-performance analog parts in what is essentially a framework for low-power digital operation, Radack admits.

Some SOI developments are already finding applications. DARPA is developing a correlator and a fast Fourier transform processor for use in radar-guided missiles or munitions. According to Radack, this particular project is using fully depleted SOI technology because it requires low power consumption coupled with very high performance.

Because fully depleted devices are extremely power efficient, they offer the potential for good handheld devices, Keast claims. This same reduction in capacitance also helps in high-power operations, making for very fast devices. Some devices on fully depleted chips process up to the 40-gigahertz range, which is useful for signal processors and radio-frequency complementary metal-oxide semiconductors that have previously used gallium arsenide or bipolar methods to achieve high performance.

While partially depleted technology is now reaching the commercial marketplace at large in the form of IBM’s chips, Keast adds that some Taiwanese and Japanese companies are already beginning to develop production methods for fully depleted semiconductors. MIT has developed several prototype devices operating at 2 volts and clocking at between 1 and 3.9 gigahertz. This effort uses transistors at the quarter-micron scale. He notes that additional research is extending this capability down to subnanometer sizes.

Through its work with fully depleted SOI, MIT is building circuits of complexity and speed approaching those of gallium arsenide, Keast says. Comparisons of two signal processing test chips, one using gallium arsenide, the other featuring SOI technology, found the SOI chip clocking at 950 megahertz and using 43 milliwatts, while the gallium-arsenide chip was slightly faster at 1 gigahertz but consumed 2 watts.

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