• Teams selected by DARPA may help revolutionize the semiconductor industry. Credit: geralt/Pixabay
     Teams selected by DARPA may help revolutionize the semiconductor industry. Credit: geralt/Pixabay

DARPA Selects Teams for $1.5 Billion Electronics Effort

July 25, 2018
By George I. Seffers
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The program is designed to boost the semiconductor industry.

The Defense Research Projects Agency (DARPA) has announced a myriad of teams from industry and academia to jumpstart innovation in the electronics industry under the approximately $1.5 billion Electronics Resurgence Initiative (ERI). The initiative is designed to nurture research in circuit design tools, advanced new materials and systems architectures through a mix of new and emerging programs.

The teams were announced at the recent three-day ERI Summit. The summit brought together about 950 members of the electronics community to explore the future of the industry and the impact this critical sector has on national defense, DARPA officials say.

Bill Chappell, the director of DARPA's Microsystems Technology Office, says the semiconductor industry is at an inflection point that includes skyrocketing costs of doing business in the electronics market mixed with the foreign investment that is flowing into the marketplace. “On top of that, we have a value chain, which is pushing more and more of the value to the application and software level away from some of the base semiconductor investments. DARPA decided that because of this confluence of events we would have a increased concentration on the basics of electronics and semiconductors,” he says.

The teams fall under three research areas: materials and integration, design and architectures.

The materials and integration area involves two programs, the Three-Dimensional Monolithic System-on-a-Chip (3DSoC) program and the Foundations Required for Novel Compute (FRANC) program. The fundamental goal is to create new means of computing vast amounts of information. The research teams have been selected to explore the roles new materials and radically different architectures can play in forming disparate chip components into larger systems. The chosen teams for the first program include researchers at the Georgia Institute of Technology and another team from Stanford University, Massachusetts Institute of Technology and SkyWater Technology Foundry, who will be working under of the 3DSoC program. Meanwhile, HRL Laboratories, Applied Materials, Ferric Inc.; University of California, Los Angeles; University of Minnesota and University of Illinois at Urbana-Champaign have been selected to take on the challenges of the FRANC program.

The research teams for the architectures research area is exploring the development of flexible architectures capable of using specialized hardware to solve specific computing problems more quickly and efficiently. The list of research teams selected for the Software Defined Hardware (SDH) program include Intel, NVIDIA, Qualcomm, STR, Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington and Princeton University. Under the Domain-Specific System on Chip (DSSoC) program, selected research teams include IBM, Oak Ridge National Labs, Arizona State University and Stanford University.

The SDH and DSSoC programs seek to explore new ways to co-optimize software and hardware without requiring more complex programming. Both programs aim to prove that there need not be a continued tradeoff between efficiency, like that found in application-specific integrated circuits.

The SDH program aims to develop hardware and software that can be reconfigured in real time based on the data being processed, adapting the computing architecture for the workload and data at hand. Researchers will investigate reconfigurable computing architectures and software environments that can deliver specialized, data-intensive application performance without sacrificing versatility or programmability, and without the need to develop specialized circuits for each application. If successful, SDH could open a pathway to data-intensive algorithms that can run at very low cost, ultimately enabling the widespread use of machine learning and artificial intelligence for Defense Department applications such as predictive logistics and decision support, as well as intelligence, surveillance and reconnaissance functions

The design research thrust area also includes two programs, the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. The goal is to create an environment that could catalyze the next wave of U.S. semiconductor innovation and broaden the competitive field for circuit design. “Right now, it can take 100 person years or more to finish a system-on-chip design, even just getting the hardware laid out, let alone writing the software on top of that hardware,” Chappell says. “The design wing looks to reduce that.” A person year is generally defined as the amount of work a person can do in one year.

The IDEA program aims to create a “no human in the loop” layout generator that would enable users with limited electronic design expertise to complete the physical design of electronic hardware within 24 hours. The software created under IDEA would be capable of automatically creating circuit design files ready for manufacturing, reducing design time from years to a single day. By applying machine learning methodologies, IDEA hopes to continuously evolve and improve the performance of the layout generator for digital circuits, mixed-signal integrated circuits, systems-in-package and printed circuit boards. 

The research teams selected to participate in the IDEA program include:

  • University of California, San Diego
  • University of Illinois at Urbana-Champaign
  • Princeton University
  • The University of Utah
  • Northrop Grumman Mission Systems
  • University of Michigan
  • Yale University
  • Cadence Design Systems
  • University of Texas at Austin
  • University of Minnesota
  • Purdue University

The POSH program seeks to significantly reduce the effort required to start a new mixed-signal system-on-a-chip design by building a foundation of verified intellectual property building blocks with known functionality. The program is designed to create an open source system-on-chip design and verification ecosystem that will enable the cost-effective design of ultra-complex systems. The teams selected include:

  • Xilinx Inc.
  • Synopsys Inc.
  • University of Southern California
  • Princeton University
  • University of Washington
  • University of Michigan
  • The University of Utah
  • LeWiz Communications
  • Brown University
  • Sandia National Laboratories
  • Stanford University
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