Digital Signal Processors Push Design, Performance Envelope
A major collaboration between communications industry giants produces cutting-edge devices.
Next-generation signal processor technology for wireless communications is the focus of a unique research center. The Atlanta-based StarCore Technology Center combines the pooled assets of Motorola Incorporated’s semiconductor products sector and Lucent Technologies’ microelectronics group.
StarCore and other such alliances are byproducts of the competition and increased momentum of the Internet age as firms join together to leverage resources and control segments of the market. The telecommunications industry is working overtime to meet worldwide demands for more mobile, connected tools and services.
Digital signal processors (DSPs) are a key component for this new wireless world. These specialized semiconductor chips perform high-speed computations with voice, data and video signals, and they are the heart of products such as cellular telephones, pagers, digital cameras, and audio and video equipment. A DSP core is a computing engine that can be used in different DSP chips regardless of the intended application. However, cores are not stand-alone products. They are part of a customized chip designed for a specific purpose.
Motorola and Lucent formed the joint research center to optimize the strong synergies both companies have in DSP development and to take advantage of their leading positions in the wireless communications system marketplace, according to Scott Beach, StarCore’s platform marketing manager. The research capabilities of Lucent’s Bell Laboratories and Motorola’s laboratories provide both companies an advantage in the early development of DSP cores.
The alliance was formed in 1998, and StarCore opened in November of that year, Beach explains. It is not a separate company or legal entity, but a research facility tasked with developing next-generation DSP cores. Because of its shared nature, all staff members are full-time Lucent or Motorola employees working in the best interest of both organizations. Wherever possible, every staff group is divided equally between the two firms, he says.
While the two companies collaborate on core designs, they separately market and develop full-fledged DSP products based on the StarCore template. Building on this platform, the companies modify the devices to meet specific product needs through the addition of memory, peripherals or additional cores, Beach explains. This process can be either collaborative or competitive as both companies compete in some markets, he notes. The alliance also allows the firms to cross-license each other’s newest cores, such as Motorola’s DSP56800 and Lucent’s DSP16000.
According to StarCore representatives, this business arrangement also will accelerate development of advanced DSP cores in a variety of industries, including communications, transportation and consumer electronics. In the consumer electronics market, advanced DSP technology will enable manufacturers to develop new products such as handheld wireless devices to access the Internet, cellular telephones with video capability, and devices with built-in speech recognition.
Beach believes that a discontinuity in wireless technology exists between second- and third-generation devices and wireline systems moving from analog to digital. For example, a DSP with 100 or 66 million instructions per second (MIPS) is sufficient for today’s second-generation wireless telephones. Beach notes that these devices handle limited amounts of data in terms of transmission—primarily voice or text displays for pagers. But as very high-speed packet data-type applications become more common, 1,000 to 2,000 MIPS is needed just to implement the standard alone. Applications such as videoconferencing or streaming video or audio require another 2,000 to 3,000 MIPS that must be added to the DSP in a portable device. All of these demands drain battery power, so the processors need low power requirements as performance increases, he observes.
StarCore released its first DSP core in April 1999. Called the SC140, it represents the first in a line of devices based on the SC100 architecture. Because it is a core, more features and capabilities will be added as it is fitted into a specific product role. The SC140 will form the basis for a series of system-on-chip products that Lucent and Motorola will release this year. Motorola’s MSC8101 is the first product based on the center’s technology to reach the market, Beach says.
Designed to accelerate the development of next-generation handheld devices and multichannel telecommunications applications, such as wireless base stations and digital subscriber line central office equipment, the SC140 combines high performance with power savings. The core delivers 3,000 MIPS or 1.2 billion multiply accumulate (MAC) operations per second while running at 300 megahertz on a 1.5-volt power supply.
Beach believes that the SC140 is the first core to fully address the balance between high performance, efficient compiling, code density and power requirements. Other manufacturers’ cores tend to stress either performance and efficient compiling or code density and energy savings—a choice that was sufficient for the last generation of cellular telephones, he observes.
As wireless devices become more capable, however, care must be taken to preserve battery life. Beach maintains that consumers will not buy a cellular telephone that can access the Internet if the battery has to be constantly recharged. This is the reason it is important to focus on performance and power savings, he says. According to StarCore representatives, in a low-power mode, a 120-megahertz, 0.9-volt SC140 can perform at 1,200 MIPS and 480 million MAC operations per second while losing only 0.066 milliamps/MIPS at 0.9 volts.
Compatibility and ease of design are other facets of the center’s approach. By using compiler-driven architecture, up to 90 percent of the software code needed to base a design on the SC140 template can be written in C or C++ instead of assembly language. These tools accelerate the time-to-market for new designs, and it becomes easier to migrate existing communications systems to higher performance levels.
Previous designs also had problems with compilers. “I think it’s clear that if you can develop these very complex replications in a higher-level language, you are going to get the product to market much faster. The problem in the DSP world is that DSPs have not been very efficient targets for compilers. They have been very complex in terms of instructions and non-orthogonal instruction sets. As a result, the compiler has not been a tool that can be used in programming,” Beach explains. In contrast, he adds that developers designed the SC140’s architecture around maximizing the performance of programs written in C from the outset.
The SC140 framework also benefits from an array of parallel processing resources that include four MAC units, four arithmetic logic units, four bit field units, two arithmetic address units, and an efficient five-stage pipeline. Based on a 16-bit orthogonal instruction—which reduces system costs for applications using serial control code—the device’s architecture is designed to use variable-length execution sets (VLES). With specific code directions to be run on a DSP core, StarCore’s VLES technology allows multiple 16-bit instructions and optional prefixes to be grouped together for single-cycle executions.
Development support is provided through a comprehensive set of baseline tools produced by StarCore. These aids are available to Motorola and Lucent under a nondisclosure agreement to support initial customer designs. The design center also has partnered with third-party developers for tools that support the SC140 core and future devices.
According to center representatives, software written for the four-MAC SC140 can be leveraged for future SC100 family implementations containing different hardware resources. Programs for the SC100 are also designed to operate on future architectures. The SC140 can interface with other DSP cores, microcontroller cores and semiprogrammable coprocessors, which are design approaches that StarCore expects to play a key role in future communications systems.
Scalability in a device is an important factor that can be modified to fit specific design requirements. Altering performance characteristics enhances system flexibility, Beach notes. “If you go in and tweak the code, focusing on high performance or time-critical kernels, you have the capability of getting down to the 6 megahertz range. That is where we show how low the SC140 optimized assembly can go. It is also scalable in the sense that it is very easy to add or subtract one or two MACs, depending on the performance levels needed,” he says.
